1. Field of the Invention
The present invention relates to the decoding of compressed images, in particular according to the MPEG standards. It more specifically relates to the data exchange between an image processing circuit and a dynamic memory.
2. Discussion of the Related Art
According to various image compression standards, in particular the MPEG standards, the images are processed by squares, the size of the squares being generally 16.times.16 pixels. To each square corresponds a so-called "macroblock". The macroblocks can have different formats. The most commonly used is the format called 4:2:0 according to which each macroblock contains four blocks of 8.times.8 luminance pixels of 8 bits and 2 blocks of 8.times.8 chrominance pixels of 8 bits.
The processed images are essentially of three types, that is, the "intra" type, the predicted type and the bi-directional type. The macroblocks of an "intra" image are not submitted to a motion compensation. In a predicted image, each macroblock can be submitted to a motion compensation which consists of combining the macroblock with another macroblock, called a predictor macroblock, fetched in a previously decoded image. Each macroblock of a bi-directional image can be submitted to a motion compensation which consists of combining the macroblock with two other predictor macroblocks respectively fetched in two previously decoded images. The locations of the predictor macroblocks are determined by motion vectors.
As it clearly appears, an MPEG decoder must store at least two previously decoded images to be able to process a bi-directional image. In fact, it also stores the currently decoded image so as to appropriately reorganize the pixels before displaying them. Indeed, the pixels are decoded block by block while they should be displayed line by line (first a field of odd lines, then a field of even lines).
FIG. 1 schematically shows an MPEG decoder discussed in European patent application 0626653. The decoder includes a dynamic memory (DRAM) accessible over a 64 bit bus B64. A pipeline circuit 12 receives compressed data over bus B64 and provides an adder 14 with the luminance and chrominance blocks of the processed macroblocks. Morever, the adder 14 receives corresponding blocks from predictor macroblocks which are supplied to a predictor circuit 16 over bus B64. Pipeline circuit 12 generally performs a variable length decoding (VLD), a run-level decoding (RLD), a conversion of zigzag scanning into linear scanning, and an inverse discrete cosine transform (DCT). According to the MPEG standards, predictor circuit 16 essentially includes a so-called "half-pixel" filter for shifting a predictor macroblock vertically and/or horizontally by half a pixel, if a motion vector for fetching this predictor macroblock is not an integer.
The decoded pixels supplied by adder 14 are stored in a buffer (FIFO) 18 before being transferred into memory 10 over bus B64.
A display circuit 20 receives pixels to displayed from memory 10 via a buffer 22.
The exchanges between memory 10 and the various decoder elements are managed by a memory control unit (MCU) 24.
Memory 10, as previously mentioned, must store two previously decoded images in order to restore a bi-directional image. In addition, a currently restored bi-directional image must also be stored in the memory to send its pixels to display 20 in an appropriate order. Thus, memory 10 includes at least three image areas IM1 to IM3. Each of these areas IM1 to IM3 must be able to store a PAL image (the largest according to the international standards) of 720.times.576 pixels. In using the 4:2:0 macroblock format, the pixels are of 12 bits and the total image size is 4,976,640 bits.
Additionally, the MPEG standards recommend that memory 10 should comprise a compressed data area CD of at least 2.6 Mbits where the compressed data wait before being processed, and an area X utilized for storing On Screen Display (OSD) information and sound data. The capacity of this area X is approximately 1 Mbit. Hence, the total capacity of memory 10 must be approximately 18 Mbits.
Such a memory is difficult to implement with current commercially available components. Indeed, the most current dynamic memory component, and thus the cheapest, has a capacity of 256 kilowords of 16 bits (256 k.times.16). With four of these components, a 16 Mbit memory accessible over a 64-bit bus is readily implemented. However, it is not advantageous to add 2 megabits accessible over the same 64-bit bus. An immediate solution would be to add 4 Mbits by connecting a component of 64 kilowords of 16 bits in parallel on each 256 k.times.16 component. However, 64 k.times.16 components are not very common and their cost to capacity ratio is particularly high.